In semiconductor technologies, a wafer undergoes various processes to form an integrated circuit. The wire routing of the integrated circuit is provided by an interconnect structure that includes numerous metal layers that are each insulated by a dielectric layer. Bonding pads are typically formed over the interconnect structure for use in wafer level testing and chip packaging (e.g., wire bonding and flip-chip). In advanced technology process (e.g., 45 nm, 32 nm, and beyond), it is desirable to implement dielectric materials having a low dielectric constant (low-k) in the interconnect structure to enhance performance. However, these low-k materials have weak mechanical strength properties which can cause peeling or cracking of the metal layers especially in a region where there is high stress such as a region underneath the bonding pad. Therefore, peeling and cracking of the metal layers can lead to poor device performance, and in some cases device failure.